Traditionally, circuits with combinational loops are found only in asynchronous designs. Combinational loops also arise in synchronous circuits as a result of automated synthesis tools converting an RTL-level description to a gate level description. In some cases, combinational loops are synthesized intentionally by a synthesis compiler for area optimization. However, combinational loops in designs are always undesirable. A combinational loop or feedback path implies a mutual dependence of a signal on itself with zero delay. Zero delay semantics necessitate special handling in designing cycle-accurate simulators or statically scheduled emulators.
In general, combinational loops breach design methodologies because they typically involve undesirable and unpredictable circuit behavior and can lead to oscillations based on the external stimuli to the loops. For designs compiled using automated synthesis-compilers, these loops are very likely to appear in generated gate-level designs. Although designs containing combinational loops can potentially save physical space when embodied in hardware, these loops are extremely difficult to manipulate in static scheduling, timing analysis, and logic minimization. Ideally, all dependencies between different signals should be known explicitly at compile time, and the value of each signal should be exclusive of its own non-delayed value.
Attempts have been made to solve the problem of combinational loops. In one approach, combinational loop analysis uses binary decision diagrams (BDDs) to detect whether a sequential circuit with combinational loops exhibits standard synchronous behavior. If so, an equivalent circuit without combinational loops is produced. In this approach, a fixed-point iteration method is used where all acyclic fragments are generated from a combinational loop that produces a well-behaved zero or one value at the output(s) of the loop. The construction of such fragments is performed using BDDs, and if all the outputs are evaluated to be stable, the BDDs are composed to form the equivalent circuit.
In another approach, it is assumed that all internal nodes are set to X (i.e., undefined), and that each of these nodes should resolve such that every combinational loop output in the circuit will be set to either a stable 0 or a stable 1. This analysis works by building all partial assignments to the inputs of the combinational loop, resulting in non-X values being assigned to the outputs of the loops. The acyclic circuit is then constructed by joining together all the partial assignment circuits, generated in the analysis. However, because this approach uses a potentially exponential algorithm, it is practical only for smaller loops.
In conventional commercial verification tools, such as cycle-precise software simulators or statically scheduled emulators, the zero delay semantic is handled by inserting a finite state machine (FSM) in a combinational loop that stalls simulation time until the outputs of the loop become stable. Another method, used in statically scheduled emulators, is to insert pipeline flops in the feedback path of a combinational loop in order to stabilize the loop output values. Such emulators force loops to become localized on a single reconfigurable chip, such as a single field-programmable gate array (FPGA). This prevents cross-chip communications from having any self-dependencies. However, multiple pipelining of a loop can cause the loop to exhibit analog behaviors, often resulting in the oscillation of otherwise non-oscillatory loops.